A fundamental shift is taking place in the fabrication of integrated circuits, and in particular in the construction of the multiple wiring layers that provide connections to the tens of millions of transistors on a state-of-the-art chip. The prior standard in the industry has been the use of aluminum wires isolated each from the other by silicon dioxide. Despite the prior success of this combination, such is now reaching the limitation imposed by state-of-the-art chips and is now placing limitations on the performance of the chips. In order to obviate these limitations, the semiconductor industry has begun a search for replacements for aluminum and/or silicon dioxide that can provide enhanced device performance.
Two shifts in fabrication of integrated circuits are currently taking place: (1) from aluminum to copper wires to reduce the resistance of the metal wires, and (2) from silicon dioxide to dielectrics with lower dielectric constants k, commonly referred to as ‘low-k’ materials. The move away from silicon dioxide as the interlayer dielectric has been driven by the need to reduce the delay times along the wires in the complex circuits. This has opened up a wide field of research and development in the semiconductor industry focused on the fabrication and characterization of new high-performance materials.
However, the stable, well-understood nature of silicon dioxide has led to an absence of effective tools and methods for characterizing dielectric materials. As a result, progress toward the identification and optimization of new dielectric materials has been slowed by the lack of characterization instruments.
In standard aluminum/silicon dioxide processes, the wiring layers are formed by first laying down a uniform aluminum film, etching away the aluminum in the regions between the wires, and then filling these regions with silicon dioxide. The switch from aluminum to copper has caused a change in this process since there is no effective way to etch copper. Thus, for copper/dielectric based integrated circuits, the Dual Damascene process is generally employed, in which two layers of dielectric material (either silicon dioxide or a low-k dielectric) are initially deposited. The dielectric layers are then etched to form vias and trenches where the wires are to be formed. The copper is then deposited into these trenches and vias. Chemical mechanical polishing (CMP) is then applied to produce a smooth surface on which the process steps can be repeated for the next wiring layer.
The Damascene process has been somewhat successful, but has also led to a wide range of problems that were not encountered in the standard Al/SiO2 technology. These problems have been particularly common when the typically less-stable low-k dielectrics are used. As an example, the dielectric etching process necessary to form the trenches for copper often damage the dielectric material causing a change in its dielectric constant, and as a consequence, a change in the performance of the device. This type of damage often occurs at the interface between the metal and dielectric and causes changes in the capacitance between wires, thus affecting device performance.
There is a clear need for dielectric metrology to be used on product wafers during manufacturing of integrated circuits and the like. The existing techniques for dielectric constant measurements of low-k films include Hg-probe, MIS-capacitance, and Corona discharge.
These techniques are able to measure k value on blanket wafers, however they cannot be used on production wafers. Moreover, Hg-probe and MIS-capacitance are not appropriate for measurements on porous dielectrics. In addition neither of the above techniques can be employed to monitor low-k dielectrics during processing.
Measuring capacitance is an important step in monitoring the fabrication process of integrated circuits. The standard method for accomplishing this task is to build large capacitance test structures directly into the device itself and then measure the capacitance of these structures by making direct contact, either through pins on the finished device or by placing small probes on contact pads.
Interdigitated comb is now a standard parametric in-line test and more representative of true low-k process metrology. However, it involves extensive sample cross-sectioning and numerical modeling, thus making the data collection unrealistically time-consuming. In addition, traditional capacitance measurements require test structures with capacitances on the order of 1–100 pF so as to overcome the stray capacitances in the measurement wires. This requirement means that interdigitated comb structures must be fairly large since the typical specific capacitance between wires in state-of-the-art integrated circuits is less than 1 fF/μm. There are three distinct disadvantages to such large capacitance test structures. First, the structures take up significant area on the wafer, which particularly undesirable on production wafers. Second, the large size of the test structure leads to significant stray capacitance between the structure and nearby structures with the stray capacitance being very difficult to account for in the analysis. Third, the large size of the structure means that the properties of interest are being averaged over large areas and therefore cannot be studied locally on the scale of the wires themselves. It therefore would be highly desirable to have a non-contact technique for capacitance measurement on miniature test structures.